Alesis QS7.1 Service Manual Page 18

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Alesis QS Series Keyboards Service Manual V1.00 11/19/06
9
shows that knowing how the hardware is supposed to respond to software changes can greatly
simplify the task of hardware troubleshooting.
The most important pins are:
D0-D16 16 Bit Data Buss (note that in the QS Series some of the other
devices only use 8 bits of the data buss. This may cause some
noise in the unused data lines during processor reads making
the appear “bad” due to a floating input. While ignored by the
software, it can make troubleshooting a real open in the data
buss more difficult.
A0-A23 23 Bit Address Buss (Note that only 20 bits are actually used).
RES System RESET line. Asserted only during power up/down. (See
Section 2.31A)
RD Read Enable
HWR Write Enable
XTAL, EXTAL Input for system clock crystal.
PX.X I/O Ports are configured by the software and allow the software
some direct hardware access. In particular are:
TXD1 Transmit Serial Data line to MIDI output circuit (See Section 2.31D).
TXD2 Transmit Serial Data line to PC/MAC output circuit (See Section 2.50).
RXD1 Receive Serial Data line From MIDI In circuit (See Section 2.31D).
RXD2 Receive Serial Data line From PC/MAC input circuit (See Section 2.50).
PITCH Pitch Wheel data input (See Section 2.31C).
DATA Data Slider data input (See Section 2.31C).
MOD Mod Wheel data input (See Section 2.31C).
RES
CD1 PCMCIA Card #1 Present Switch input (See Section 2.32B).
CD2 PCMCIA Card #2 Present Switch input (See Section 2.32B).
PC/MAC PC/MAC Serial Port Switch input (See Section 2.50).
KEYINT Keyscan ASIC interrupt .input (See Section 2.33).
SUS Sustain Pedal Input.
SMUTE DAC Output Mute
EDIT PCB SWITCH MATRIX (See Section 2.31C).
2.31A RESET
Reset is one of the single most important circuits/signals in the entire unit. Without a
correct RST signal during power up and power down, any number of problems can occur.
These can range from an occasional failure such as an odd audio “blip”, to complete, system
wide lock ups and data corruption. Therefore any time processor problems are suspected, RST
should be the first thing checked.
In order to ensure that data will not be corrupted, the reset circuit uses the raw power
supply signal to determine the correct time to assert the RST signal (i.e. not until the regulated
+5V supply rail contains no ripple). This is done by using a raw supply threshold of
approximately 7V. Since the power down sequence of events is generally the reverse of the
power up process, only the power up events are described here.
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